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TRIO ADIONO

Institut Teknologi Bandung S3 - Teknik Elektro dan Informatika SINTA ID : 6033680
9.839
SINTA Score Overall
1.284
SINTA Score 3Yr
9.839
Affil Score
1.284
Affil Score 3Yr
Latest number of publications
  Scopus Analysis  

Characterization of A2G UAV communication channels under rician fading conditions
Q2 as Journal Indonesian Journal of Electrical Engineering and Computer Science
Author Order : 2 of 6     Creator : Guno Y.
2025 0 cited
Parallel and Pipeline Multicore OFDM Baseband Processor for Wideband UOWC Systems
Q1 as Journal IEEE Transactions on Circuits and Systems I Regular Papers
Author Order : 1 of 7     Creator : Adiono T.
2025 0 cited
Design and implementation of a real-time SDR-FPGA-based versatile radio frequency OFDM system
Q2 as Journal Integration
Author Order : 0 of 7     Creator : Adiono T.
2025 0 cited
Hardware-Software Stitching Algorithm in Lightweight Q-Learning System on Chip (SoC) for Shortest Path Optimization
Q1 as Journal IEEE Access
Author Order : 4 of 4     Creator : Salomo Y.
2025 0 cited
Reconfigurable Radix-2/4/8 of Unified 2N Points NTT-INTT for Homomorphic Encryption
Q3 as Conference Proceedin Proceedings IEEE International Symposium on Circuits and Systems
Author Order : 6 of 6     Creator : Syafalni I.
2025 0 cited
Base Conversion RNS using Hybrid Barret-Karatsuba-Based Modulus Prime Cores for Homomorphic Multiplication
Q3 as Conference Proceedin Proceedings IEEE International Symposium on Circuits and Systems
Author Order : 6 of 6     Creator : Hasanuddin M.O.
2025 0 cited
Low Complexity and Scalable Architecture of Dual-Mode Training and Inference Hardware Accelerator for Deep Q-Network (DQN) Based Edge Computing
Q1 as Journal IEEE Access
Author Order : 5 of 5     Creator : Sumarudin A.
2025 0 cited
Optimizing Deep Q-Network for Shortest Path Computation of Mobile Robot Agents
no-Q as Conference Proceedin Apsipa ASC 2024 Asia Pacific Signal and Information Processing Association Annual Summit and Confere
Author Order : 5 of 5     Creator : Sumarudin A.
2024 0 cited
Physical Design of RISC-V based System-on-Chip using OpenLane
no-Q as Conference Proceedin Apccas and Primeasia 2024 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE As
Author Order : 7 of 8     Creator : Fauzan M.
2024 2 cited
A Scalable Design of a Full-Stack Real-Time OFDM Baseband Processor for Network-Enabled VLC Systems
Q1 as Journal IEEE Access
Author Order : 1 of 7     Creator : Adiono T.
2024 3 cited
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Summary

Article Quartile
Research Output
  Scopus GScholar WOS
Article 330 427 122
Citation 1676 3087 370
Cited Document 251 312 73
H-Index 19 26 11
i10-Index 51 100 13
G-Index 1 1 6
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